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1M x 32-Bit Dynamic RAM Module (2M x 16-Bit Dynamic RAM Module)
HYM 321160S/GS-60/-70
Advanced Information
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1 048 576 words by 32-bit organization (alternative 2 097 152 words by 16-bit) Fast access and cycle time 60 ns access time 110 ns cycle time (-60 version) 70 ns access time 130 ns cycle time (-70 version) Fast page mode capability with 40 ns cycle time (-60 version) 45 ns cycle time (-70 version) Single + 5 V ( 10 %) supply Low power dissipation max. 4840 mW active (-60 version) max. 4400 mW active (-70 version) CMOS - 44 mW standby TTL - 88 mW standby CAS-before-RAS refresh, RAS-only-refresh, Hidden refresh 8 decoupling capacitors mounted on substrate All inputs, outputs and clock fully TTL compatible 72 pin Single in-Line Memory Module Utilizes eight 1M x 4-DRAMs in 300 mil SOJ packages 1024 refresh cycles /16 ms Optimized for use in byte-write non-parity applications Tin-Lead contact pads (S- version) Gold contact pads (GS - version) single sided module with 25.4 mm (1000 mil) height
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Semiconductor Group
1
6.94
HYM 321160S/GS-60/-70 1M x 32-Bit
The HYM 321160S/GS-60/-70 is a 4 MByte DRAM module organized as 1 048 576 words by 32bit in a 72-pin single-in-line package comprising eight HYB 514400BJ 1M x 4 DRAMs in 300 mil wide SOJ-packages mounted together with eight 0.2 F ceramic decoupling capacitors on a PC board. The HYM 321160S/GS-60/-70 can also be used as a 2 097 152 words by 16-bits dynamic RAM module by means of connecting DQ0 and DQ16, DQ1 and DQ17, DQ2 and DQ18, ..., DQ15 and DQ31, respectively. Each HYB 514400BJ is described in the data sheet and is fully electrically tested and processed according to Siemens standard quality procedure prior to module assembly. After assembly onto the board, a further set of electrical tests is performed. The speed of the module can be detected by the use of four presence detect pins. The common I/O feature on the HYM 321160S/GS-60/-70 dictates the use of early write cycles. Ordering Information Type HYM 321160S-60 HYM 321160S-70 HYM 321160GS-60 HYM 321160GS-70 Ordering Code Q67100-Q2010 on request Q67100-Q2009 on request Package L-SIM-72-11 L-SIM-72-11 L-SIM-72-11 L-SIM-72-11 Descriptions DRAM module (access time 60 ns) DRAM module (access time 70 ns) DRAM module (access time 60 ns) DRAM module (access time 70 ns)
Semiconductor Group
2
HYM 321160S/GS-60/-70 1M x 32-Bit
Pin Names
VSS DQ16 DQ17 DQ18 DQ19 N.C. A1 A3 A5 N.C. DQ20 DQ21 DQ22 DQ23 N.C. A8 N.C. N.C. 1 DQ0 2 3 DQ1 4 5 DQ2 6 7 DQ3 8 9 VCC 10 11 A0 12 13 A2 14 15 A4 16 17 A6 18 19 DQ4 20 21 DQ5 22 23 DQ6 24 25 DQ7 26 27 A7 28 29 VCC 30 31 A9 32 33 RAS2 34 35 N.C. 36
A0-A9 DQ0-DQ31 CAS0 - CAS3 RAS0, RAS2 WE
Address Inputs Data Input/Output Column Address Strobe Row Address Strobe Read/Write Input Power (+ 5 V) Ground Presence Detect Pin No Connection
VCC VSS
PD N.C.
N.C. VSS CAS2 CAS1 N.C. WE DQ8 DQ9 DQ10 DQ11 DQ12 VCC DQ13 DQ14 DQ15 PD0 PD2 N.C.
37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71
N.C. 38 CAS0 40 CAS3 42 RAS0 44 N.C. 46 N.C. 48 DQ24 50 DQ25 52 DQ26 54 DQ27 56 DQ28 58 DQ29 60 DQ30 62 DQ31 64 N.C. 66 PD1 68 PD3 70 VSS 72
Presence Detect Pins -60 PD0 PD1 PD2 PD3 -70
VSS VSS
N.C. N.C.
VSS VSS VSS
N.C.
Pin Configuration
Semiconductor Group
3
HYM 321160S/GS-60/-70 1M x 32-Bit
RAS0 CAS0 DQ0-DQ3 CAS RAS I/O1-I/O4 OE D0 CAS RAS I/O1-I/O4 OE D1
DQ4-DQ7 CAS1 DQ8-DQ11
CAS RAS I/O1-I/O4 OE D2 CAS RAS I/O1-I/O4 OE D3
DQ12-DQ15
RAS2 CAS2 CAS RAS I/O1-I/O4 OE D4 CAS RAS I/O1-I/O4 OE D5
DQ16-DQ19 DQ20-DQ23
CAS3 CAS RAS I/O1-I/O4 OE D6 CAS RAS I/O1-I/O4 D7 OE
DQ24-DQ27 DQ28-DQ31
A0-A9 WE
D0-D7 D0-D7
VCC VSS
C0 - C7
Block Diagram
Semiconductor Group
4
HYM 321160S/GS-60/-70 1M x 32-Bit
Absolute Maximum Ratings Operating temperature range ......................................................................................... 0 to + 70 C Storage temperature range...................................................................................... - 55 to + 125 C Input/output voltage ........................................................................................................ - 1 to + 7 V Power supply voltage...................................................................................................... - 1 to + 7 V Power dissipation................................................................................................................... 6.16 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Characteristics 1) TA = 0 to 70 C; VCC = 5 V 10 % Parameter Input high voltage Input low voltage Output high voltage (IOUT = - 5 mA) Output low voltage (IOUT = 4.2 mA) Input leakage current (0 V < VIN < 6.5 V, all other pins = 0 V) Output leakage current (DO is disabled, 0 V < VOUT < 5.5 V) Average VCC supply current: -60 version -70 version (RAS, CAS, address cycling, tRC = tRC min.) Standby VCC supply current (RAS = CAS = VIH) Symbol Limit Values min. max. 5.5 0.8 - 0.4 20 10 V V V V A A 2.4 - 1.0 2.4 - - 20 - 10 Unit Test Condition - - - - - -
VIH VIL VOH VOL II(L) IO(L) ICC1
- -
880 800
mA mA
2), 3)
ICC2
-
16
mA
-
Average VCC supply current during RAS ICC3 only refresh cycles: -60 version -70 version (RAS cycling, CAS = VIH , tRC = tRC min.)
2)
- -
880 800
mA mA
Semiconductor Group
5
HYM 321160S/GS-60/-70 1M x 32-Bit
DC Characteristics (cont'd) 1) Parameter Symbol Limit Values min. Average VCC supply current during fast ICC4 page mode: -60 version -70 version (RAS = VIL, CAS, address cycling tPC = tPC min.) Standby VCC supply current (RAS = CAS = VCC - 0.2 V) max. Unit Test Condition
2), 3)
- -
560 560
mA mA
ICC5
-
8
mA
-
ICC6 Average VCC supply current during CAS-before-RAS refresh mode: -60 version -70 version
(RAS, CAS cycling, tRC = tRC min.)
1)
- -
880 800
mA mA
Capacitance TA = 0 to 70 C; VCC = 5 V 10 %; f = 1 MHz Parameter Input capacitance (A0 to A9) Input capacitance (RAS0, RAS2) Input capacitance (CAS0-CAS3) Input capacitance (WE) I/O capacitance (DQ0-DQ31)
. .
Symbol min.
Limit Values max. 70 35 35 45 20 - - - - -
Unit pF pF pF pF pF
CI1 CI2 CI3 CI4 CIO1
Semiconductor Group
6
HYM 321160S/GS-60/-70 1M x 32-Bit
AC Characteristics 5)6) TA = 0 to 70 C,VCC = 5 V 10 %, tT = 5 ns Parameter
Symbol
M16F
Limit Values -50 min. max. - - 10k 10k - - - - 37 25 min. 110 40 60 15 0 10 0 15 20 15 15 60 - 50 16 5 3 - -60 max. - - 10k 10k - - - - 45 30 - - - 50 16
Unit
Note
common parameters
Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) Refresh period tRC tRP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tT tREF 90 30 50 13 0 8 0 10 18 13 13 50 5 3 - ns ns ns ns ns ns ns ns ns ns ns ns ns ms 7
Read Cycle
Access time from RAS Access time from CAS Access time from column address Column address to RAS lead time Read command setup time Read command hold time Read command hold time referenced to RAS CAS to output in low-Z Output buffer turn-off delay tRAC tCAC tAA tRAL tRCS tRCH tRRH tCLZ tOFF - - - 25 0 0 0 0 0 50 13 25 - - - - - 13 - - - 30 0 0 0 0 0 60 15 30 - - - - - 15 ns ns ns ns ns ns ns ns ns 11 11 8 12 8, 9 8, 9 8,10
Semiconductor Group
7
HYM 321160S/GS-60/-70 1M x 32-Bit
AC Characteristics (cont'd) 5)6) TA = 0 to 70 C,VCC = 5 V 10 %, tT = 5 ns Parameter
Symbol
M16F
Limit Values -50 min. max. - - - - - - - min. 10 10 0 15 15 0 10 -60 max. - - - - - - -
Unit
Note
Early Write Cycle
Write command hold time Write command pulse width Write command setup time Write command to RAS lead time Write command to CAS lead time Data setup time Data hold time tWCH tWP tWCS tRWL tCWL tDS tDH 8 8 0 13 13 0 10 ns ns ns ns ns ns ns 14 14 13
Fast Page Mode Cycle
Fast page mode cycle time CAS precharge time Access time from CAS precharge RAS pulse width CAS precharge to RAS Delay tPC tCP tCPA tRAS tRHCP 35 10 - 50 30 - - 30 200k - 40 10 - 60 35 - - 35 200k - ns ns ns ns ns 7
CAS-before-RAS Refresh Cycle
CAS setup time CAS hold time RAS to CAS precharge time Write to RAS precharge time Write hold time referenced to RAS tCSR tCHR tRPC tWRP tWRH 10 10 5 10 10 - - - - - 10 10 5 10 10 - - - - - ns ns ns ns ns
Semiconductor Group
8
HYM 321160S/GS-60/-70 1M x 32-Bit
Notes 1) All voltages are referenced to VSS . 2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. 4) An initial pause of 200 s is required after power-up followed by 8 RAS cycles out of which at least one cycle has to be a refresh cycle before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 5) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL . 6) Measured with a load equivalant of 2 TTL loads and 100 pF. 7) tOFF (max.) defines the time at which the output achieves the open-circuit condition and is not referenced to output voltage levels. 8) Either tRCH or tRRH must be satisfied for a read cycle. 9) These parameters are referenced to the CAS leading edge. 10) tWCS is not a restrictive operating parameter. This is included in the data sheet as electrical characteristic only. If tWCS > tWCS (min.), the cycle is an early write cycle and data out pin will remain open circuit (high impedance). 11) Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC . 12) Operation within the tRAD (max.) limit insures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA . 13) For CAS-before-RAS cycles only.
Semiconductor Group
9
HYM 321160S/GS-60/-70 1M x 32-Bit
Package Outlines L-SIM-72-11 Module package (Single-in-line single sided memory module)
Semiconductor Group
10

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